Chip Startup Raises $135M, Aiming to Address AI’s Key Challenge in Memory Rather Than Compute

When you ask a question to ChatGPT, it triggers a fast data relay operation. Information leaves memory, is preprocessed by a CPU, sent for extensive calculations to a GPU, and returns — this entire sequence occurs for each word the AI generates.

The efficiency challenge is rooted in the structure — it requires navigation through some of the most expensive and energy-intensive chips for each request. XCENA, a startup with offices in South Korea and the U.S., seeks to tackle this issue. Established four years ago, XCENA has developed a chip that brings computing power much closer to DRAM — the fast, short-term memory chips actively used by processors — allowing routine data tasks to take place near memory, thus eliminating costly trips between CPUs, GPUs, and memory.

If successfully scaled, this breakthrough could substantially reduce AI infrastructure costs, which explains the excitement from investors all over the country. Recently, XCENA secured $135 million in a Series B funding round, elevating its valuation to $570 million and total funding to $185 million.

XCENA’s CEO, Jin Kim, co-founded the company in 2022 along with CTO Dohun Kim and CPO Harry Juhyun Kim, all of whom are seasoned industry professionals from Samsung and SK Hynix, the memory giants that supply chips for Nvidia’s GPUs. “Although CPUs and GPUs have advanced over time, memory has not. XCENA intends to change that,” Kim said in an interview with TechCrunch. “The recent rise in memory prices and stocks points to a more significant shift towards memory-centric architectures in AI infrastructure,” he added. (This month, the three leading companies in the global memory chip industry — Samsung, SK Hynix, and Micron — each surpassed a trillion-dollar valuation for the first time.)

XCENA’s business model is based on the insight that “inference is not just a computational issue; it is increasingly becoming a memory scaling problem,” Kim explained.

The MX1 chip from XCENA connects to the CPU via CXL (Compute Express Link) — essentially an expedited route between the processor and memory — processing data before it needs to leave the memory unit. This method brings computation closer to the data. The company claims that what used to require 10 servers could now potentially function on just one.

“While GPUs are excellent at matrix multiplications — the complex calculations underpinning AI model training — much of the related data management, such as preprocessing, KV cache management [the system that retains previous conversation context to avoid reprocessing], and data caching, still operates on CPUs. Our chip manages these tasks directly within the memory module itself,” Kim continued.

There has been a surge in demand for memory solutions since the latter half of last year, and the company is optimistic about its timing.

The company is engaging in initial discussions with several global memory vendors, though Kim withheld their names. XCENA’s target customers are hyperscalers investing tens of billions annually in AI infrastructure, where even minor improvements in memory efficiency could result in significant savings.

Currently, the MX1 is in the prototype stage. Mass production is scheduled to begin at Samsung’s foundries by the end of 2026, with revenue expected to start flowing in by 2027.

While manufacturers of neural processing units (NPUs) compete with Nvidia for training workloads, XCENA focuses on the essential memory-intensive layer that supports it all.

XCENA’s closest rivals include Astera Labs and Marvell, both publicly traded companies pioneering next-gen memory connectivity solutions. According to Kim, Marvell is an established player in this sector, and XCENA’s edge lies in its intellectual property. “We leverage thousands of cores,” Kim said, in contrast to Marvell’s approach, which relies on fewer general-purpose cores, as indicated by publicly available data.

These cores implement RISC-V — an open-source chip design framework — and are specifically fine-tuned for data processing, with each core designed to be compact and efficient. In addition to the cores, XCENA develops its own internal memory hierarchy, interconnect bus, and DRAM controller — a level of vertical integration that most chip companies, including larger competitors, typically delegate.

Seoul-based venture capital firms Altinum and IMM Investment co-led the Series B funding round alongside Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company, with over 90 employees across its offices in Pangyo, a technology hub near Seoul, and Sunnyvale, is also engaged in discussions with international investors for additional funding.